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aec q100 grade 1 compliant this product conforms to specifications per the terms of the ramtron standard warranty. the product has completed ramtrons internal qualification testing and has reached production status. cypress semiconductor corporation ? 198 champion court ? san jose, ca 95134 - 1709 ? 408 - 943 - 2600 document number: 001 - 86149 rev. * a revised may 07 , 2013 fm25 cl64b C automotive temp. 64kb serial 3v f - ram memory features 64k bit ferroelectric nonvolatile ram organized as 8,192 x 8 bits high endurance 10 trillion (10 13 ) read/writes nodelay? writes advanced high - reliability ferro electric process fast serial peripheral interface - spi up to 16 m hz frequency direct hardware replacement for eeprom spi mode 0 & 3 (cpol, cpha=0,0 & 1,1) sophisticated write protection scheme hardware protection software protection low power consu mption low voltage operation 3.0 - 3.6 v 6 a standby current (+85 c) industry standard configuration automotive temperature - 40 c to +125 c o qualified to aec q100 specification green /rohs 8 - pin soic description the fm25 cl64b is a 64 - kilobit nonvolatile memory employing an advanced ferroelectric process. a ferroelectric random access memory or fram is nonvolatile and performs reads and writes like a ram. it provide s reliable data retention for years while eliminating the complexities, overhead, and system level reliability problems caused by eeprom and other nonvolatile memories. the fm25cl64b performs write operations at bus speed. no write delays are incurred. data is written to the memory array immediately after each byte has been transferred to the d evice. the next bus cycle may commence without the need for data polling. the fm25cl64b is capable of supporting 10 13 read/write cycles, or 10 million times more write cycles than eeprom. these capabilities make the fm25 cl64b ideal for nonvolatile memory applications requiring frequent or rapid writes. examples range from data collection, where the number of write cycles may be critical, to demanding automotive controls where the long write time of eeprom can cause data loss. the fm25 cl64b provides subs tantial benefits to users of serial eeprom as a hardware drop - in replacement. the fm25 cl64b uses the high - speed spi bus, which enhances the high - speed write capability of fram technology. device specifications are guaranteed over the automotive temperature range of - 40c to +125 c. pin configuration pin name function /cs chip select /wp write protect /hold hold sck serial clock si serial data input so serial data output vdd supply voltage vss ground ordering information fm25 cl64b - ga green /rohs 8 - pin soic , automotive grade 1 fm25cl64b - gatr green/rohs 8 - pin soic, automotive grade 1, tape & reel cs so wp vss vdd hold sck si 1 2 3 4 8 7 6 5
fm25cl64b - automotive temp. document number: 001 - 8 6149 rev. * a page 2 of 1 5 figure 1. block diagram pin descriptions pin name i/o description /cs input chip select: this active lo w input activates the device. when high, the device enters low - power standby mode, ignores other inputs, and all outputs are tri - stated. when low, the device internally activates the sck signal. a falling edge on /cs must occur prior to every op - code. sc k input serial clock: all i/o activity is synchronized to the serial clock. inputs are latched on the rising edge and outputs occur on the falling edge. since the device is static, the clock frequency may be any value between 0 and 16 mhz and may be interr upted at any time. /hold input hold: the /hold pin is used when the host cpu must interrupt a memory operation for another task. when /hold is low, the current operation is suspended. the device ignores any transition on sck or /cs. all transitions on /h old must occur while sck is low. /wp input write protect: this active low pin prevents write operations to the status register . this is critical since other write protection features are controlled through the status register . a complete explanation of write protection is provided below. *note that the function of /wp is different from the fm25040 where it prevents all writes to the part. si input serial input: all data is input to the device on this pin. the pin is sampled on the rising edge of sck a nd is ignored at other times. it should always be driven to a valid logic level to meet idd specifications. * si may be connected to so for a single pin data interface. so output serial output: this is the data output pin. it is driven during a read and remains tri - stated at all other times including when /hold is low. data transitions are driven on the falling edge of the serial clock. * so may be connected to si for a single pin data interface. vdd supply power supply ( 3.0 v to 3.6 v) vss supply ground instruction decode clock generator control logic write protect instruction register address register counter ` 1 , 024 x 64 fram array 13 data i / o register 8 nonvolatile status register 3 wp cs hold sck so si
fm25cl64b - automotive temp. document number: 001 - 8 6149 rev. * a page 3 of 1 5 overview the fm25 cl64b is a serial fram memory. the memory array is logically organized as 8,192 x 8 and is accessed using an industry standard serial peripheral interface or spi bus. functional operation of the fram is similar to serial eeproms. the m ajor difference between the fm25 cl64b and a serial eeprom with the same pinout is the fram?s superior write performance. memory architecture when accessing the fm25 cl64b , the user addresses 8,192 locations of 8 data bits each. these data bits are shifted serially. the addresses are accessed using the spi protocol, which includes a chip select (to permit multiple devices on the bus), an op - code, and a two - byte address. the upper 3 bits of the address range are ?don?t care? values. the complete address of 13 - bits specifies each byte address uniquely. most functions of the fm25 cl64b either are controlled by the spi interface or are handled automatically by on - board circuitry. the access time for memory operation is essentially zero, beyond the time needed fo r the serial protocol. that is, the memory is read or written at the speed of the spi bus. unlike an eeprom, it is not necessary to poll the device for a ready condition since writes occur at bus speed. so, by the time a new bus transaction can be shifted into the device, a write operation will be complete. this is explained in more detail in the interface section. users expect several obvious system benefits from the fm25 cl64b due to its fast write cycle and high endurance as compared with eeprom. in add ition there are less obvious benefits as well. for example in a high noise environment, the fast - write operation is less susceptible to corruption than an eeprom since it is completed quickly. by contrast, an eeprom requiring milliseconds to write is vulne rable to noise during much of the cycle. note that the fm25 cl64b contains no power management circuits other than a simple internal power - on reset. it is the user?s responsibility to ensure that vdd is within datasheet tolerances to prevent incorrect ope ration. serial peripheral interface C spi bus the fm25 cl64b employs a serial peripheral interface (spi) bus. it is specified to operate at speeds up to 16 mhz. this high - speed serial bus provides high performance serial communication to a host microcont roller. many common microcontrollers have hardware spi ports allowing a direct interface. it is quite simple to emulate the port using ordinary port pins for microcontrollers that do not. the fm25 cl64b operates in spi mode 0 and 3. the spi interface uses a total of four pins: clock, data - in, data - out, and chip select. it is possible to connect the two data pins together. figure 2 illustrates a typical system configuration using the fm25 cl64b with a microcontroller that offers an spi port. figure 3 shows a similar configuration for a microcontroller that has no hardware support for the spi bus. protocol overview the spi interface is a synchronous serial interface using clock and data pins. it is intended to support multiple devices on the bus. each device is activated using a chip select. once chip select is activated by the bus master, the fm25 cl64b will begin monitoring the clock and data lines. the relationship between the falling edge of /cs, the clock and data is dictated by the spi mode. the device wi ll make a determination of the spi mode on the falling edge of each chip select. while there are four such modes, the fm25 cl64b supports modes 0 and 3. figure 4 shows the required signal relationships for modes 0 and 3. for both modes, data is clocked in to the fm25 cl64b on the rising edge of sck and data is expected on the first rising edge after /cs goes active. if the clock begins from a high state, it will fall prior to beginning data transfer in order to create the first rising edge. the spi protoco l is controlled by op - codes. these op - codes specify the commands to the device. after /cs is activated the first byte transferred from the bus master is the op - code. following the op - code, any addresses and data are then transferred. note that the wren and wrdi op - codes are commands with no subsequent data transfer. important: t he /cs pin must go inactive after an operation is complete and before a new op - code can be issued. there is one valid op - code only per active chip select.
fm25cl64b - automotive temp. document number: 001 - 8 6149 rev. * a page 4 of 1 5 figure 2. system configuration with spi port figure 3. system configuration without spi port spi mode 0: cpol=0, cpha=0 spi mode 3: cpol=1, cpha=1 figure 4. spi mo des 0 & 3 f m 2 5 c l 6 4 b m o s i : m a s t e r o u t , s l a v e i n m i s o : m a s t e r i n , s l a v e o u t s s : s l a v e s e l e c t s o s i s c k c s h o l d f m 2 5 c l 6 4 b s o s i s c k c s h o l d s p i m i c r o c o n t r o l l e r s s 1 s s 2 h o l d 1 h o l d 2 m i s o m o s i s c k m i c r o c o n t r o l l e r f m 2 5 c l 6 4 b s o s i s c k c s h o l d 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
fm25cl64b - automotive temp. document number: 001 - 8 6149 rev. * a page 5 of 1 5 data transfer all data transfers to and from the fm25 cl64b occur in 8 - bit groups. they are synchronized to the clock signal (sck), and they transfer most significant bit (msb) first. serial inputs are registered on the rising edge of sck. outpu ts are driven from the falling edge of sck. command structure there are six commands called op - codes that can be issued by the bus master to the fm25 cl64b . they are listed in the table below. these op - codes control the functions performed by the memory. they can be divided into three categories. first, there are commands that have no subsequent operations. they perform a single function such as to enable a write operation. second are commands followed by one byte, either in or out. they operate on the st atus register . the third group includes commands for memory transactions followed by address and one or more bytes of data. table 1. op - code commands name description op - code wren set write enable latch 0000 0110b wrdi write disable 0000 0100b rdsr re ad status register 0000 0101b wrsr write status register 0000 0001b read read memory data 0000 0011b write write memory data 0000 0010b wren - set write enable latch the fm25 cl64b will power up with writes disabled. the wren command must be issued p rior to any write operation. sending the wren op - code will allow the user to issue subsequent op - codes for write operations. these include writing the status register and writing the memory. sending the wren op - code causes the internal write enable latch to be set. a flag bit in the status register , called wel, indicates the state of the latch. wel=1 indicates that writes are permitted. attempting to write the wel bit in the status register has no effect. completing any write operation will automatically clear the write - enable latch and prevent further writes without another wren command. figure 5 below illustrates the wren command bus configuration. wrdi - write disable the wrdi command disables all write activity by clearing the write enable latch. the user can verify that writes are disabled by reading the wel bit in the status register and verifying that wel=0. figure 6 illustrates the wrdi command bus configuration. figure 5. wren bus configuration figure 6. wrdi bus configuration
fm25cl64b - automotive temp. document number: 001 - 8 6149 rev. * a page 6 of 1 5 rdsr - read status register the rdsr command allows the bus master to verify the contents of the status register. reading status provides information about the current state of the write protection features. following the rdsr op - code, the fm25 cl64b will return one byte with the contents of the status register. the status register is described in detail in a later section. wrsr C write status register the wrsr command allows the user to select certain write protection features by writing a byte to the status register. prior to issuing a wrsr command, the /wp pin must be high or inactive. note that on the fm25 cl64b , /wp only prevents writing to the status register, not the memory array. prior to sending the wrsr command, the use r must send a wren command to enable writes. note that executing a wrsr command is a write operation and therefore clears the write enable latch. figure 7. rdsr bus configuration figure 8. wrsr bus configura tion (wren not shown) status register & write protection the write protection features of the fm25 cl64b are multi - tiered. first, a wren op - code must be issued prior to any write operation. assuming that writes are enabled using wren, writes to memory ar e controlled by the status register. as described above, writes to the status register are performed using the wrsr command and subject to the /wp pin. the status register is organized as follows. table 2. status register bit 7 6 5 4 3 2 1 0 name wpen 0 0 0 bp1 bp0 wel 0 bits 0 and 4 - 6 are fixed at 0 and cannot be modified. note that bit 0 ( ready in eeproms) is unnecessary as the fram writes in real - time and is never busy. the wpen, bp1 and bp0 control write protection features. they a re nonvolatile ( shaded yellow). the wel flag indicates the state of the write enable latch. attempting to directly write the wel bit in the status register has no effect on its state. this bit is internally set and cleared via the wren and wrdi commands, respectively. bp 1 and bp0 are memory block write protection bits. they specify portions of memory that are write protected as shown in the following table. table 3. block memory write protection bp1 bp0 protected address range 0 0 none 0 1 1800h to 1fffh (upper ?) 1 0 1000h to 1fffh (upper ?) 1 1 0000h to 1fffh (all)
fm25cl64b - automotive temp. document number: 001 - 8 6149 rev. * a page 7 of 1 5 the bp1 and bp0 bits and the write enable latch are the only mechanisms that protect the memory from writes. the remaining write protection features protect inadvertent changes to the block protect bit s. the wpen bit controls the effect of the hardware /wp pin. when wpen is low, the /wp pin is ignored. when wpen is high, the /wp pin controls write access to the status register . thus the status register is write protected if wpen=1 and /wp=0. this sc heme provides a write protection mechanism, which can prevent software from writing the memory under any circumstances. this occurs if the bp1 and bp0 are set to 1, the wpen bit is set to 1, and /wp is set to 0. this occurs because the block protect bits prevent writing memory and the /wp signal in hardware prevents altering the block protect bits (if wpen is high). therefore in this condition, hardware must be involved in allowing a write operation. the following table summarizes the write protection cond itions. table 4. write protection wel wpen /wp protected blocks unprotected blocks status register 0 x x protected protected protected 1 0 x protected unprotected unprotected 1 1 0 protected unprotected protected 1 1 1 protected unprotected unprotect ed memory operation the spi interface, which is capable of a relatively high clock frequency, highlights the fast write capability of the fram technology. unlike spi - bus eeproms, the fm25 cl64b can perform sequential writes at bus speed. no page registe r is needed and any number of sequential writes may be performed. write operation all writes to the memory array begin with a wren op - code. the next op - code is the write instruction. this op - code is followed by a two - byte address value. the upper 3 - bits of the address are ignored. in total, the 13 - bits specify the address of the first data byte of the write operation. subsequent bytes are data and they are written sequentially. addresses are incremented internally as long as the bus master continues to is sue clocks. if the last address of 1fffh is reached, the counter will roll over to 0000h. data is written msb first. a write operation is shown in figure 9. unlike eeproms, any number of bytes can be written sequentially and each byte is written to memory immediately after it is clocked in (after the 8 th clock). the rising edge of /cs terminates a write op - code operation. read operation after the falling edge of /cs, the bus master can issue a read op - code. following this instruction is a two - byte addres s value. the upper 3 - bits of the address are ignored. in total, the 13 - bits specify the address of the first byte of the read operation. after the op - code and address are complete, the si line is ignored. the bus master issues 8 clocks, with one bit read o ut for each. addresses are incremented internally as long as the bus master continues to issue clocks. if the last address of 1fffh is reached, the counter will roll over to 0000h. data is read msb first. the rising edge of /cs terminates a read op - code op eration. a read operation is shown in figure 10. hold the /hold pin can be used to interrupt a serial operation without aborting it. if the bus master pulls the /hold pin low while sck is low, the current operation will pause. taking the /hold pin high w hile sck is low will resume an operation. the transitions of /hold must occur while sck is low, but the sck pin can toggle during a hold state.
fm25cl64b - automotive temp. document number: 001 - 8 6149 rev. * a page 8 of 1 5 figure 9. memory write (wren not shown) figure 10. me mory read endurance the fm25cl64b devices are capable of being accessed at least 10 1 3 times, reads or writes. an f - ram memory operates with a read and restore mechanism. therefore, an endurance cycle is applied on a row basis for each access (read or write) to the memory array. the f - ram architecture is based on an array of rows and columns. rows are defined by a12 - a3 and column addresses by a2 - a0. see block diagram (pg 2) which shows the array as 1k rows of 64 - bits each. the entire row is internally accessed once whether a single byte or all eight bytes are read or written. each byte in the row is counted only once in an endurance calculation. the table below shows endurance calculations for 64 - byte repeating loop, which includes an op - code, a starti ng address, and a sequential 64 - byte data stream. this causes each byte to experience one endurance cycle through the loop. f - ram read and write endurance is virtually unlimited even at 10mhz clock rate. table 5. time to reach endurance limit for re peating 64 - byte loop sck freq (mhz) endurance cycles/sec. endurance cycles/year years to reach limit 10 18,660 5.88 x 10 1 1 17.0 5 9,33 0 2.94 x 10 1 1 34.0 1 1,870 5.88 x 10 1 0 170.1 0 1 2 3 4 5 6 7 0 1 2 3 4 5 3 4 5 6 7 0 1 2 3 4 5 6 7 o p - c o d e 0 0 0 0 0 0 1 0 m s b 1 3 - b i t a d d r e s s x x x 1 2 1 1 1 0 4 3 2 1 0 7 6 5 4 3 2 1 0 l s b m s b l s b c s s c k s i s o d a t a 0 1 2 3 4 5 6 7 0 1 2 3 4 5 3 4 5 6 7 0 1 2 3 4 5 6 7 o p - c o d e 0 0 0 0 0 0 1 m s b 1 3 - b i t a d d r e s s x x x 1 2 1 1 1 0 4 3 2 1 0 7 6 5 4 3 2 1 0 l s b m s b l s b c s s c k s i s o d a t a 1
fm25cl64b - automotive temp. document number: 001 - 8 6149 rev. * a page 9 of 1 5 electrical specifications absolute maximum ratings symbol description ratings v dd power supply voltage with respect to v ss - 1.0v to +5.0v v in voltage on any pin with respect to v ss - 1.0v to +5.0v and v in < v dd +1.0v t stg storage temperature - 55 c to + 12 5 c t lead lead temperature (soldering, 10 seconds) 26 0 c v esd elec trostatic discharge voltage - human body model (aec - q100 - 002 rev. e) - charged device model (aec - q100 - 011 rev. b) - machine model ( a ec - q100 - 003 rev. e ) 4kv 1.25kv 300v package moisture sensitivity level msl - 1 stresses above those listed under a bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational secti on of this specification is not implied. exposure to absolute maximum ratings conditions for extended periods may affect device reliability. dc operating conditions ( t a = - 40 c to +125 c, v dd = 3.0 v to 3.6 v unless otherwise specified) symbol parameter min typ max units notes v dd power supply voltage 3.0 3.3 3.6 v i dd vdd supply current @ sck = 1.0 mhz @ sck = 16 .0 mhz - - 0.3 3 ma ma 1 i sb standby current @ + 85 c @ + 125 c - - 6 20 a a 2 i li input leakage current - 1 a 3 i lo output leakage current - 1 a 3 v ih input high voltage 0.7 5 v dd v dd + 0.3 v v il input low voltage - 0.3 0.25 v dd v v oh output high voltage @ i oh = - 2 ma v dd C 0.5 - v v ol output low voltage @ i ol = 2 ma - 0.4 v v hys input hyst eresis 0.05 v dd - v 4 notes 1. sck toggling between v dd - 0.3v and v ss , other inputs v ss or v dd - 0.3v. 2. sck = si = /cs=v dd . all inputs v ss or v dd . 3. v ss v in v dd and v ss v out v dd . 4. characterized but not 100% tested in production. applies only to /cs and sc k pins.
fm25cl64b - automotive temp. document number: 001 - 8 6149 rev. * a page 10 of 1 5 ac parameters ( t a = - 40 c to +125 c, v dd = 3.0v to 3.6v unless otherwise specified ) symbol parameter min max units notes f ck sck clock frequency 0 16 mhz t ch clock high time 25 ns 1 t cl clock low time 25 ns 1 t csu chip select setup 10 ns t csh chip select hold 10 ns t od output disable time 20 ns 2 t odv output data valid time 25 ns t oh output hold time 0 ns t d deselect time 60 ns t r data in rise time 50 ns 2,3 t f data in fall time 50 ns 2,3 t su data setup time 5 ns t h data hold time 5 ns t hs /hold setup time 10 ns t hh /hold hold time 10 ns t hz /hold low to hi - z 20 ns 2 t lz /hold high to data active 20 ns 2 notes 1. t ch + t cl = 1/f ck . 2. characterized but not 100% tested in production. 3. rise and fall times meas ured b etween 10% and 90% of waveform. capacitance ( t a = 25 c, f=1.0 mhz, v dd = 3.3v) symbol parameter min max units notes c o output c apacitance (so) - 8 pf 1 c i input c apacitance - 6 pf 1 notes 1. this parameter is periodically sampled and not 100% test ed. ac test conditions input pulse levels 10% and 90% of v dd input and output timing levels 0.5 v dd input rise and fall times 5 ns output load capacitance 30 pf power cycle timing power cycle timing ( t a = - 40 c to + 125 c, v dd = 3.0v to 3.6v unless otherwise specified ) symbol parameter min max units notes t pu v dd (min) to first access start 1 - m s t pd last access complete to v dd (min) 0 - s t vr v dd rise time 30 - s/v 1 t vf v dd fall time 2 0 - s/v 1 notes 1. sl ope mea sured at any point on v dd waveform . v d d m i n t p u v d d c s t v r t p d t v f
fm25cl64b - automotive temp. document number: 001 - 8 6149 rev. * a page 11 of 1 5 serial data bus timing /hold timing data retention ( v dd = 3.0v to 3.6v unless otherwise specified) automotive grade ss retention experiment results os retention ae c - q100 grade 3 aec - q100 grade 2 aec - q100 grade 1 unlimited unlimited unlimited 10.9 yrs @ 85 o c 5.5 years @ 105 o c 11,2 00 hours @ 125 o c 10 years 5 years 11k hours note : data retention qualification tests are accelerated tests and are performed such t hat all three conditions have been applied : (1) 10 years at a temperature of +8 5 c, (2) 5 years at +105 c, and (3) 1 1 ,000 hours at +125 c. 1 / f c k t c l t c h t c s h t o d v t o h t o d t c s u t s u t h t d t r t f
fm25cl64b - automotive temp. document number: 001 - 8 6149 rev. * a page 12 of 1 5 opposite state data retention graphs for grade 1, 2 and 3 automotive: the se specifications can be used for dif ferent multi - temperature thermal profiles. e xample of a n aec C q100 g rade 1 automotive f - ram application. temperature ( t ) time factor ( t ) profile life time l( p ) t1 = 125 o c t2 = 105 o c t3 = 85 o c t4 = 55 o c 10% 15% 25% 50% > 10.46 years
fm25cl64b - automotive temp. document number: 001 - 8 6149 rev. * a page 13 of 1 5 mechanical drawing 8 - pin soic (jedec standard ms - 012 variation aa) refer to jedec ms - 012 for complete dimensions and notes. all dimensions in millimeters . soic package marking scheme legend: xxxxxxx = part number, p = package type, t = temp (a = automotive grade, blank = ind.) rr = rev code, lllll = lot code, z = package code ric = ramtron i nt?l corp, yy = year, ww = work week = pb - free example: fm 25cl64b, green/rohs soic, automotive temperature rev. ba, lot 64179, soic year 2013, work week 07 pb - free 25 cl64b - ga ba 6 4179 s ric1307 xxxxxxx - pt rrlllll z ricyyww pin 1 3 . 90 0 . 10 6 . 00 0 . 20 4 . 90 0 . 10 0 . 10 0 . 25 1 . 35 1 . 75 0 . 33 0 . 51 1 . 27 0 . 10 mm 0 . 25 0 . 50 45 0 . 40 1 . 27 0 . 19 0 . 25 0 - 8 recommended pcb footprint 7 . 70 0 . 65 1 . 27 2 . 00 3 . 70
fm25cl64b - automotive temp. document number: 001 - 8 6149 rev. * a page 14 of 1 5 revision history revision date summary 1.0 2/18/2011 initial release. 1.1 5/3/2011 added esd ratings. 3.0 9/12/2011 changed to production status. 3.1 3/31/2012 improved t pu and t vf specs. 3.2 10/31/2012 changed retention specifications document history document title: fm2 5cl64b 64k b serial 3v f - ram memory ( automotive temp) document number: 001 - 8 6149 revision ecn orig. of change submission date description of change ** 3912930 gvch 02/25/2013 new spec *a 3985108 gvch 0 5 / 0 7 /2013 updated soic package marking scheme
fm25cl64b - automotive temp. document number: 001 - 8 6149 rev. * a page 15 of 1 5 sales, solu tions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distributors. to find the office closest to you, visit us at cypress locations . products automotive cypress.com/go /a utomotive clocks & buff ers cypress.com/go/clocks interface cypress.com/go /i nterface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/ go/psoc touch sensing cypress.com/go/touch usb controllers cypress.com/go/usb psoc ? solutions psoc.cypress.com/so lutions psoc 1 | psoc 3 | psoc 5 cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support ramtron is a registered trademark and nodelay? is a trademark of cypress semiconductor corp. all other trademarks or registered trademarks referenced herein are the property of their respective owners. ? cypress semi conductor corporation, 2011 - 2013 . the information contained herein is su bject to change without notice. cypress semiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress p roduct. nor does it convey or imply any license under patent or other rights. cypress produ cts are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypress. furthermore, cypress does not authorize its products for use as cri tical components in life - support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life - support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. this source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and s ubject to worldwide patent protection (united states and foreign), united states copyright laws and international treaty provisions. cypress hereby grants to licensee a personal, non - exclusive, non - transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and deri vative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translat ion, compilation, or representation of this source code except as specified above is prohibited without the express written p ermission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, includin g, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to the materials described herein. cypress does no t assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authorize its products for use as critical components in life - support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress product in a life - support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cyp ress software license agreement .

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